Multi-line bash commands in makefile

Question

Considering that every command is run in its own shell  what is the best way to run a multi-line bash command in a makefile  For example  like this  for i in  find  do     all  quot  all  i quot  done gcc  all

User · Accepted Answer

You can use backslash for line continuation. However note that the shell receives the whole command concatenated into a single line, so you also need to terminate some of the lines with a semicolon:

foo:
    for i in `find`;     \
    do                   \
        all="$$all $$i"; \
    done;                \
    gcc $$all

But if you just want to take the whole list returned by the find invocation and pass it to gcc, you actually don't necessarily need a multiline command:

foo:
    gcc `find`

Or, using a more shell-conventional $(command) approach (notice the $ escaping though):

foo:
    gcc $$(find)

User · Answer

As indicated in the question  every sub-command is run in its own shell   This makes writing non-trivial shell scripts a little bit messy -- but it is possible   The solution is to consolidate your script into what make will consider a single sub-command  a single line    Tips for writing shell scripts within makefiles    Escape the script s use of   by replacing with    Convert the script to work as a single line by inserting   between commands If you want to write the script on multiple lines  escape end-of-line with   Optionally start with set -e to match make s provision to abort on sub-command failure This is totally optional  but you could bracket the script with    or    to emphasize the cohesiveness of a multiple line sequence -- that this is not a typical makefile command sequence   Here s an example inspired by the OP   mytarget              set -e        msg  header          for i in    seq 1 3    do msg    msg pre    i  post    done        msg    msg  footer         echo msg   msg

User · Answer

Of course  the proper way to write a Makefile is to actually document which targets depend on which sources   In the trivial case  the proposed solution will make foo depend on itself  but of course  make is smart enough to drop a circular dependency   But if you add a temporary file to your directory  it will  magically  become part of the dependency chain   Better to create an explicit list of dependencies once and for all  perhaps via a script   GNU make knows how to run gcc to produce an executable out of a set of  c and  h files  so maybe all you really need amounts to  foo    wildcard   h    wildcard   c

User · Answer

What s wrong with just invoking the commands   foo         echo line1        echo line2               And for your second question  you need to escape the   by using    instead  i e  bash -c      echo   a        EDIT  Your example could be rewritten to a single line script like this   gcc   for i in  find   do echo  i  done

User · Answer

The ONESHELL directive allows to write multiple line recipes to be executed in the same shell invocation  all  foo  SOURCE FILES     shell find   -name    c     ONESHELL  foo    SOURCE FILES      FILES        for F in     do         FILES      F       done     gcc  quot    FILES     quot  -o     There is a drawback though   special prefix characters              -     and          are interpreted differently  https   www gnu org software make manual html node One-Shell html

[bash] Multi-line bash commands in makefile

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