SyntaxFix

[operator-keyword] ' << ' operator in verilog

<< is a binary shift, shifting 1 to the left 8 places.

4'b0001 << 1 => 4'b0010

>> is a binary right shift adding 0's to the MSB.
>>> is a signed shift which maintains the value of the MSB if the left input is signed.

4'sb1011 >>  1 => 0101
4'sb1011 >>> 1 => 1101

Three ways to indicate left operand is signed:

module shift;
  logic        [3:0] test1 = 4'b1000;
  logic signed [3:0] test2 = 4'b1000;

  initial begin
    $display("%b", $signed(test1) >>> 1 ); //Explicitly set as signed
    $display("%b", test2          >>> 1 ); //Declared as signed type
    $display("%b", 4'sb1000       >>> 1 ); //Signed constant
    $finish;
  end
endmodule

Examples related to operator-keyword

• What does double question mark (??) operator mean in PHP • How to use comparison operators like >, =, < on BigDecimal • What do >> and << mean in Python? • How do operator.itemgetter() and sort() work? • ' << ' operator in verilog • Overloading operators in typedef structs (c++) • C++ Double Address Operator? (&&) • Concatenating strings doesn't work as expected

Examples related to verilog

• Verilog: How to instantiate a module • ' << ' operator in verilog • Verilog generate/genvar in an always block • Assign a synthesizable initial value to a reg in Verilog • Using wire or reg with input or output in Verilog • How to declare and use 1D and 2D byte arrays in Verilog? • What do curly braces mean in Verilog?