Using wire or reg with input or output in Verilog

Question

When you declare something as input or output  how do you know if you have to also declare it as a reg or a wire

User · Answer

seeing it in digital circuit domain

A Wire will create a wire output which can only be assigned any input by using assign statement as assign statement creates a port/pin connection and wire can be joined to the port/pin
A reg will create a register(D FLIP FLOP ) which gets or recieve inputs on basis of sensitivity list either it can be clock (rising or falling ) or combinational edge .

so it completely depends on your use whether you need to create a register and tick it according to sensitivity list or you want to create a port/pin assignment

User · Answer

reg and wire specify how the object will be assigned and are therefore only meaningful for outputs   If you plan to assign your output in sequential code such as within an always block  declare it as a reg  which really is a misnomer for  variable  in Verilog   Otherwise  it should be a wire  which is also the default

User · Answer

basically reg is used to store values For example if you want a counter which will count and thus will have some value for each count  we will use a reg  On the other hand if we just have a plain signal with 2 values 0 and 1 we will declare it as wire Wire can t hold values So assigning values to wire leads to problems

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The Verilog code compiler you use will dictate what you have to do  If you use illegal syntax  you will get a compile error   An output must also be declared as a reg only if it is assigned using a  procedural assignment    For example   output reg a  always    a   b    There is no need to declare an output as a wire   There is no need to declare an input as a wire or reg

User · Answer

An output reg foo is just shorthand for output foo wire  reg foo  assign foo wire   foo   It s handy when you plan to register that output anyway   I don t think input reg is meaningful for module  perhaps task    input wire and output wire are the same as input and output  it s just more explicit

[verilog] Using wire or reg with input or output in Verilog

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