When you declare something as input or output, how do you know if you have to also declare it as a reg
or a wire
?
This question is related to
verilog
basically reg is used to store values.For example if you want a counter(which will count and thus will have some value for each count),we will use a reg. On the other hand,if we just have a plain signal with 2 values 0 and 1,we will declare it as wire.Wire can't hold values.So assigning values to wire leads to problems....
An output reg foo
is just shorthand for output foo_wire; reg foo; assign foo_wire = foo
. It's handy when you plan to register that output anyway. I don't think input reg
is meaningful for module
(perhaps task
). input wire
and output wire
are the same as input
and output
: it's just more explicit.
The Verilog code compiler you use will dictate what you have to do. If you use illegal syntax, you will get a compile error.
An output
must also be declared as a reg
only if it is assigned using a "procedural assignment". For example:
output reg a;
always @* a = b;
There is no need to declare an output
as a wire
.
There is no need to declare an input
as a wire
or reg
.
seeing it in digital circuit domain
so it completely depends on your use whether you need to create a register and tick it according to sensitivity list or you want to create a port/pin assignment
Source: Stackoverflow.com