Verilog How to instantiate a module

Question

If I have a Verilog module  top  and a verilog module  subcomponent  how do I instantiate subcomponent in top   top   module top     input        clk     input        rst n     input        enable     input   9 0  data rx 1     input   9 0  data rx 2     output  9 0  data tx 2      subcomponent   module subcomponent     input        clk     input        rst n     input   9 0  data rx     output  9 0  data tx      Note This was written as a generic question that keeps cropping up now and again  it is following the self-answer format  Addition answers and updates are encouraged

User · Answer

Be sure to check out verilog-mode and especially verilog-auto. http://www.veripool.org/wiki/verilog-mode/ It is a verilog mode for emacs, but plugins exist for vi(m?) for example.

An instantiation can be automated with AUTOINST. The comment is expanded with M-x verilog-auto and can afterwards be manually edited.

subcomponent subcomponent_instance_name(/*AUTOINST*/);

Expanded

subcomponent subcomponent_instance_name (/*AUTOINST*/
  //Inputs
  .clk,         (clk)           
  .rst_n,       (rst_n)
  .data_rx      (data_rx_1[9:0]),
  //Outputs
  .data_tx      (data_tx[9:0])
);

Implicit wires can be automated with /*AUTOWIRE*/. Check the link for further information.

User · Answer

This is all generally covered by Section 23 3 2 of SystemVerilog IEEE Std 1800-2012   The simplest way is to instantiate in the main section of top  creating a named instance and wiring the ports up in order   module top     input        clk     input        rst n     input        enable     input   9 0  data rx 1     input   9 0  data rx 2     output  9 0  data tx 2     subcomponent subcomponent instance name     clk  rst n  data rx 1  data tx      endmodule   This is described in Section 23 3 2 1 of SystemVerilog IEEE Std 1800-2012   This has a few draw backs especially regarding the port order of the subcomponent code  simple refactoring here can break connectivity or change behaviour  for example if some one else fixs a bug and reorders the ports for some reason  switching the clk and reset order  There will be no connectivity issue from your compiler but will not work as intended   module subcomponent    input        rst n           input        clk          It is therefore recommended to connect using named ports  this also helps tracing connectivity of wires in the code   module top     input        clk     input        rst n     input        enable     input   9 0  data rx 1     input   9 0  data rx 2     output  9 0  data tx 2     subcomponent subcomponent instance name      clk clk    rst n rst n    data rx data rx 1    data tx data tx       endmodule   This is described in Section 23 3 2 2 of SystemVerilog IEEE Std 1800-2012   Giving each port its own line and indenting correctly adds to the readability and code quality    subcomponent subcomponent instance name      clk        clk             input    rst n      rst n           input    data rx    data rx 1       input   9 0     data tx    data tx         output  9 0       So far all the connections that have been made have reused inputs and output to the sub module and no connectivity wires have been created  What happens if we are to take outputs from one component to another   clk gen      clk        clk sub         output    en         enable          input  subcomponent subcomponent instance name      clk        clk sub         input    rst n      rst n           input     data rx    data rx 1       input   9 0     data tx    data tx         output  9 0       This nominally works as a wire for clk sub is automatically created  there is a danger to relying on this  it will only ever create a 1 bit wire by default  An example where this is a problem would be for the data   Note that the instance name for the second component has been changed  subcomponent subcomponent instance name      clk        clk sub         input    rst n      rst n           input     data rx    data rx 1       input   9 0     data tx    data temp       output  9 0     subcomponent subcomponent instance name2      clk        clk sub         input    rst n      rst n           input     data rx    data temp       input   9 0     data tx    data tx         output  9 0       The issue with the above code is that data temp is only 1 bit wide  there would be a compile warning about port width mismatch  The connectivity wire needs to be created and a width specified  I would recommend that all connectivity wires be explicitly written out   wire  9 0  data temp subcomponent subcomponent instance name      clk        clk sub         input    rst n      rst n           input     data rx    data rx 1       input   9 0     data tx    data temp       output  9 0     subcomponent subcomponent instance name2      clk        clk sub         input    rst n      rst n           input     data rx    data temp       input   9 0     data tx    data tx         output  9 0       Moving to SystemVerilog there are a few tricks available that save typing a handful of characters  I believe that they hinder the code readability and can make it harder to find bugs   Use  port with no brackets to connect to a wire reg of the same name  This can look neat especially with lots of clk and resets but at some levels you may generate different clocks or resets or you actually do not want to connect to the signal of the same name but a modified one and this can lead to wiring bugs that are not obvious to the eye    module top     input        clk     input        rst n     input        enable     input   9 0  data rx 1     input   9 0  data rx 2     output  9 0  data tx 2     subcomponent subcomponent instance name      clk                        input   Auto connect      rst n                      input   Auto connect      data rx    data rx 1       input   9 0     data tx    data tx         output  9 0      endmodule   This is described in Section 23 3 2 3 of SystemVerilog IEEE Std 1800-2012   Another trick that I think is even worse than the one above is    which connects unmentioned ports to signals of the same wire  I consider this to be quite dangerous in production code  It is not obvious when new ports have been added and are missing or that they might accidentally get connected if the new port name had a counter part in the instancing level  they get auto connected and no warning would be generated   subcomponent subcomponent instance name                                   Auto connect      data rx    data rx 1       input   9 0     data tx    data tx         output  9 0       This is described in Section 23 3 2 4 of SystemVerilog IEEE Std 1800-2012

[verilog] Verilog: How to instantiate a module

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