Assign a synthesizable initial value to a reg in Verilog

20

I'm an FPGA noob trying to learn Verilog. How can I "assign" a value to a reg in an always block, either as an initial value, or as a constant. I'm trying to do something like this in the code below. I get an error because the 8 bit constant doesn't count as input. I also don't want to trigger the always off of a clock. I just want to assign a register to a specific value. As I want it to be synthesisable I can't use an initial block. Thanks a lot.

module top
(
    input wire clk,
    output wire [7:0] led   
 );


reg [7:0] data_reg ; 
always @*
begin
    data_reg = 8'b10101011;
end

assign led = data_reg;

endmodule

This question is tagged with verilog

~ Asked on 2012-04-04 05:30:22

The Best Answer is


31

You can combine the register declaration with initialization.

reg [7:0] data_reg = 8'b10101011;

Or you can use an initial block

reg [7:0] data_reg;
initial data_reg = 8'b10101011;

~ Answered on 2012-04-04 17:48:56


6

The other answers are all good. For Xilinx FPGA designs, it is best not to use global reset lines, and use initial blocks for reset conditions for most logic. Here is the white paper from Ken Chapman (Xilinx FPGA guru)

http://japan.xilinx.com/support/documentation/white_papers/wp272.pdf

~ Answered on 2014-03-18 17:32:53


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