VHDL - How should I create a clock in a testbench

Question

How should I create a clock in a testbench  I already have found one answer  however others on stack overflow have suggested that there are alternative or better ways of achieving this   LIBRARY ieee  USE ieee std logic 1164 ALL   ENTITY test tb IS  END test tb   ARCHITECTURE behavior OF test tb IS      COMPONENT test         PORT clk   IN std logic       END COMPONENT      signal clk   std logic     0      constant clk period   time    1 ns   BEGIN     uut  test PORT MAP  clk   gt  clk              -- Clock process definitions  clock with 50  duty cycle is generated here     clk process  process    begin         clk  lt    0           wait for clk period 2   --for 0 5 ns signal is  0           clk  lt    1           wait for clk period 2   --for next 0 5 ns signal is  1      end process   END     source here

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My favoured technique   signal clk   std logic     0   -- make sure you initialise      clk  lt   not clk after half period    I usually extend this with a finished signal to allow me to stop the clock   clk  lt   not clk after half period when finished     1  else  0       Gotcha alert  Care needs to be taken if you calculate half period from another constant by dividing by 2   The simulator has a  time resolution  setting  which often defaults to nanoseconds    In which case  5 ns   2 comes out to be 2 ns so you end up with a period of 4ns  Set the simulator to picoseconds and all will be well  until you need fractions of a picosecond to represent your clock time anyway

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How to use a clock and do assertions  This example shows how to generate a clock  and give inputs and assert outputs for every cycle  A simple counter is tested here   The key idea is that the process blocks run in parallel  so the clock is generated in parallel with the inputs and assertions   library ieee  use ieee std logic 1164 all   entity counter tb is end counter tb   architecture behav of counter tb is     constant width   natural    2      constant clk period   time    1 ns       signal clk   std logic     0       signal data   std logic vector width-1 downto 0       signal count   std logic vector width-1 downto 0        type io t is record         load   std logic          data   std logic vector width-1 downto 0           count   std logic vector width-1 downto 0       end record      type ios t is array  natural range  lt  gt   of io t      constant ios   ios t                1    00    00              0    UU    01              0    UU    10              0    UU    11               1    10    10              0    UU    11              0    UU    00              0    UU    01          begin     counter 0  entity work counter port map  clk  load  data  count        process     begin         for i in ios range loop             load  lt   ios i  load              data  lt   ios i  data              wait until falling edge clk               assert count   ios i  count          end loop          wait      end process       process     begin         for i in 1 to 2   ios length loop             wait for clk period   2              clk  lt   not clk          end loop          wait      end process  end behav    The counter would look like this   library ieee  use ieee std logic 1164 all  use ieee numeric std all  -- unsigned  entity counter is     generic           width   in natural    2            port           clk  load   in std logic          data   in std logic vector width-1 downto 0           count   out std logic vector width-1 downto 0         end entity counter   architecture rtl of counter is     signal cnt   unsigned width-1 downto 0   begin     process clk  is     begin         if rising edge clk  then             if load    1  then                 cnt  lt   unsigned data               else                 cnt  lt   cnt   1              end if          end if      end process      count  lt   std logic vector cnt   end architecture rtl    Related  https   electronics stackexchange com questions 148320 proper-clock-generation-for-vhdl-testbenches

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Concurrent signal assignment   library ieee  use ieee std logic 1164 all   entity foo is end  architecture behave of foo is     signal clk  std logic     0   begin CLOCK  clk  lt     1  after 0 5 ns when clk    0  else          0  after 0 5 ns when clk    1   end       ghdl -a foo vhdl   ghdl -r foo --stop-time 10ns --wave foo ghw   ghdl info  simulation stopped by --stop-time   gtkwave foo ghw       Simulators simulate processes and it would be transformed into the equivalent process to your process statement   Simulation time implies the use of wait for or after when driving events for sensitivity clauses or sensitivity lists

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If multiple clock are generated with different frequencies  then clock generation can be simplified if a procedure is called as concurrent procedure call   The time resolution issue  mentioned by Martin Thompson  may be mitigated a little by using different high and low time in the procedure   The test bench with procedure for clock generation is   library ieee  use ieee std logic 1164 all   entity tb is end entity   architecture sim of tb is    -- Procedure for clock generation   procedure clk gen signal clk   out std logic  constant FREQ   real  is     constant PERIOD      time    1 sec   FREQ         -- Full period     constant HIGH TIME   time    PERIOD   2           -- High time     constant LOW TIME    time    PERIOD - HIGH TIME   -- Low time  always  gt   HIGH TIME   begin     -- Check the arguments     assert  HIGH TIME    0 fs  report  clk plain  High time is zero  time resolution to large for frequency  severity FAILURE      -- Generate a clock cycle     loop       clk  lt    1         wait for HIGH TIME        clk  lt    0         wait for LOW TIME      end loop    end procedure     -- Clock frequency and signal   signal clk 166   std logic    signal clk 125   std logic   begin    -- Clock generation with concurrent procedure call   clk gen clk 166  166 667E6    -- 166 667 MHz clock   clk gen clk 125  125 000E6    -- 125 000 MHz clock    -- Time resolution show   assert FALSE report  Time resolution     amp  time image time succ 0 fs   severity NOTE   end architecture    The time resolution is printed on the terminal for information  using the concurrent assert last in the test bench   If the clk gen procedure is placed in a separate package  then reuse from test bench to test bench becomes straight forward   Waveform for clocks are shown in figure below     An more advanced clock generator can also be created in the procedure  which can adjust the period over time to match the requested frequency despite the limitation by time resolution   This is shown here   -- Advanced procedure for clock generation  with period adjust to match frequency over time  and run control by signal procedure clk gen signal clk   out std logic  constant FREQ   real  PHASE   time    0 fs  signal run   std logic  is   constant HIGH TIME     time    0 5 sec   FREQ   -- High time as fixed value   variable low time v    time                     -- Low time calculated per cycle  always  gt   HIGH TIME   variable cycles v      real    0 0              -- Number of cycles   variable freq time v   time    0 fs             -- Time used for generation of cycles begin   -- Check the arguments   assert  HIGH TIME    0 fs  report  clk gen  High time is zero  time resolution to large for frequency  severity FAILURE    -- Initial phase shift   clk  lt    0     wait for PHASE    -- Generate cycles   loop     -- Only high pulse if run is  1  or  H      if  run    1   or  run    H   then       clk  lt   run      end if      wait for HIGH TIME      -- Low part of cycle     clk  lt    0       low time v    1 sec     cycles v   1 0    FREQ  - freq time v - HIGH TIME   --   1 0 for cycle after current     wait for low time v      -- Cycle counter and time passed update     cycles v    cycles v   1 0      freq time v    freq time v   HIGH TIME   low time v    end loop  end procedure    Again reuse through a package will be nice

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