I had always used this for detecting a rising edge:
if (clk'event and clk='1') then
but this can also be used:
if rising_edge(clk) then
Reading this post, rising_edge(clk)
is recommended, but there is also a comment indicating that rising_edge(clk)
could lead to wrong behaviour.
I can't decide which one to choose for the future, going on with (clk'event and clk='1')
or adopting rising_edge(clk)
.
Any real-world expereince on these two? Any preferences?
Thanks!
This question is related to
vhdl
Practical example:
Imagine that you are modelling something like an I2C bus (signals called SCL
for clock and SDA
for data), where the bus is tri-state and both nets have a weak pull-up. Your testbench should model the pull-up resistor on the PCB with a value of 'H'.
scl <= 'H'; -- Testbench resistor pullup
Your I2C master or slave devices can drive the bus to '1' or '0' or leave it alone by assigning a 'Z'
Assigning a '1' to the SCL net will cause an event to happen, because the value of SCL changed.
If you have a line of code that relies on (scl'event and scl =
'1')
, then you'll get a false trigger.
If you have a line of code that relies on rising_edge(scl)
, then
you won't get a false trigger.
Continuing the example: you assign a '0' to SCL, then assign a 'Z'. The SCL net goes to '0', then back to 'H'.
Here, going from '1' to '0' isn't triggering either case, but going from '0' to 'H' will trigger a rising_edge(scl)
condition (correct), but the (scl'event and scl = '1')
case will miss it (incorrect).
General Recommenation:
Use rising_edge(clk)
and falling_edge(clk)
instead of clk'event
for all code.
The linked comment is incorrect : 'L' to '1' will produce a rising edge.
In addition, if your clock signal transitions from 'H' to '1', rising_edge(clk)
will (correctly) not trigger while (clk'event and clk = '1')
(incorrectly) will.
Granted, that may look like a contrived example, but I have seen clock waveforms do that in real hardware, due to failures elsewhere.
rising_edge is defined as:
FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND (To_X01(s) = '1') AND
(To_X01(s'LAST_VALUE) = '0'));
END;
FUNCTION To_X01 ( s : std_ulogic ) RETURN X01 IS
BEGIN
RETURN (cvt_to_x01(s));
END;
CONSTANT cvt_to_x01 : logic_x01_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
If your clock only goes from 0 to 1, and from 1 to 0, then rising_edge will produce identical code. Otherwise, you can interpret the difference.
Personally, my clocks only go from 0 to 1 and vice versa. I find rising_edge(clk)
to be more descriptive than the (clk'event and clk = '1')
variant.
Source: Stackoverflow.com