shift a std logic vector of n bit to right or left

Question

I have a vector signal tmp   std logic vector 15 downto 0   I have to shift it to left or right of n bit  how can I realize this operation  I thought to concatenation operation but I didn t know how use it

User · Answer

add Pbl  lt   to stdlogicvector to bitvector dato cu 25 downto 2   sll 1   add Pbl is a std logic vector of 24 bit dato cu is a std logic vector of 32 bit   First  you need to convert the std logic vector with to bitvector   function because sll statement works with logic 1 and 0 bits

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Personally  I think the concatenation is the better solution  The generic implementation would be  entity shifter is     generic           REGSIZE    integer    8       port          clk        in  str logic          Data in    in  std logic          Data out   out std logic REGSIZE-1 downto 0   end shifter    architecture bhv of shifter is     signal shift reg   std logic vector REGSIZE-1 downto 0      others lt   0    begin     process  clk  begin         if rising edge clk  then             shift reg  lt   shift reg REGSIZE-2 downto 0   amp  Data in          end if      end process  end bhv  Data out  lt   shift reg    Both will implement as shift registers  If you find yourself in need of more shift registers than you are willing to spend resources on  EG dividing 1000 numbers by 4  you might consider using a BRAM to store the values and a single shift register to contain  indices  that result in the correct shift of all the numbers

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There are two ways that you can achieve this  Concatenation  and shift rotate functions    Concatenation is the  manual  way of doing things  You specify what part of the original signal that you want to  keep  and then concatenate on data to one end or the other  For example  tmp  lt   tmp 14 downto 0   amp   0   Shift functions  logical  arithmetic   These are generic functions that allow you to shift or rotate a vector in many ways  The functions are  sll  shift left logical   srl  shift right logical    A logical shift inserts zeros  Arithmetric shifts  sra sla  insert the left most or right most bit  but work in the same way as logical shift  Note that for all of these operations you specify what you want to shift  tmp   and how many times you want to perform the shift  n bits  Rotate functions  rol  rotate left   ror  rotate right   Rotating does just that  the MSB ends up in the LSB and everything shifts left  rol  or the other way around for ror    Here is a handy reference I found  see the first page

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This is typically done manually by choosing the appropriate bits from the vector and then appending 0s   For example  to shift a vector 8 bits  variable tmp   std logic vector 15 downto 0      tmp    x 00   amp  tmp 15 downto 8     Hopefully this simple answer is useful to someone

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Use the ieee numeric std library  and the appropriate vector type for the numbers you are working on  unsigned or signed     Then the operators are sla sra for arithmetic shifts  ie fill with sign bit on right shifts and lsb on left shifts  and sll srl for logical shifts  ie fill with  0 s    You pass a parameter to the operator to define the number of bits to shift   A  lt   B srl 2  -- logical shift right 2 bits     Update   I have no idea what I was writing above  thanks to Val for pointing that out    Of course the correct way to shift signed and unsigned types is with the shift left and shift right functions defined in ieee numeric std   The shift and rotate operators sll  ror etc are for vectors of boolean  bit or std ulogic  and can have interestingly unexpected behaviour in that the arithmetic shifts duplicate the end-bit even when shifting left   And much more history can be found here   http   jdebp eu  FGA bit-shifts-in-vhdl html  However  the answer to the original question is still  sig  lt   tmp sll number of bits

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I would not suggest to use sll or srl with std logic vector    During simulation sll gave me  U  value for those bits  where I expected 0 s    Use shift left    shift right   functions   For example   OP1   in std logic vector 7 downto 0   signal accum  std logic vector 7 downto 0    accum  lt   std logic vector shift left unsigned accum   to integer unsigned OP1       accum  lt   std logic vector shift right unsigned accum   to integer unsigned OP1

[vhdl] shift a std_logic_vector of n bit to right or left

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