Makefiles with source files in different directories

Question

I have a project where the directory structure is like this                             projectroot                                                --------------- ----------------                                                               part1           part2            part3                                                           ------ -----       --- ----         --- -----                                                              data    src   inc   src      inc    src        inc    How should I write a makefile that would be in part src  or wherever really   that could comple link on the c c   source files in part  src    Can I do something like -I projectroot part1 src -I projectroot part1 inc -I projectroot part2 src      If that would work  is there an easier way to do it   I ve seen projects where there is a makefile in each of the corresponding part  folders    in this post I used the question mark like in bash syntax

User · Answer

I think it s better to point out that using Make  recursive or not  is something that usually you may want to avoid  because compared to today tools  it s difficult to learn  maintain and scale   It s a wonderful tool but it s direct use should be considered obsolete in 2010     Unless  of course  you re working in a special environment i e  with a legacy project etc   Use an IDE  CMake or  if you re hard cored  the Autotools     edited due to downvotes  ty Honza for pointing out

User · Answer

I suggest to use autotools        Place generated object files   o  into the same directory as their source files  in order to avoid collisions when non-recursive make is used   AUTOMAKE OPTIONS   subdir-objects   just including it in Makefile am with the other quite simple stuff   Here is the tutorial

User · Answer

I was looking for something like this and after some tries and falls i create my own makefile  I know that s not the  idiomatic way  but it s a begining to understand make and this works for me  maybe you could try in your project   PROJ NAME mono  CPP FILES   shell find   -name    cpp    S OBJ   patsubst   cpp    o    CPP FILES    CXXFLAGS -c            -g           -Wall  all    PROJ NAME       echo Running application      echo          PROJ NAME     PROJ NAME     S OBJ       echo Linking objects         g   -o          o    cpp   h      echo Compiling and generating object             g     lt    CXXFLAGS  -o     main o  main cpp      echo Compiling and generating object             g     lt    CXXFLAGS   clean       echo Removing secondary things      rm -r -f objects   S OBJ    PROJ NAME       echo Done    I know that s simple and for some people my flags are wrong  but as i said this is my first Makefile to compile my project in multiple dirs and link all of then together to create my bin   I m accepting sugestions  D

User · Answer

The VPATH option might come in handy  which tells make what directories to look in for source code  You d still need a -I option for each include path  though  An example   CXXFLAGS -Ipart1 inc -Ipart2 inc -Ipart3 inc VPATH part1 src part2 src part3 src  OutputExecutable  part1api o part2api o part3api o   This will automatically find the matching partXapi cpp files in any of the VPATH specified directories and compile them  However  this is more useful when your src directory is broken into subdirectories  For what you describe  as others have said  you are probably better off with a makefile for each part  especially if each part can stand alone

User · Answer

The traditional way is to have a Makefile in each of the subdirectories  part1  part2  etc   allowing you to build them independently  Further  have a Makefile in the root directory of the project which builds everything   The  root  Makefile would look something like the following    all         MAKE  -C part1        MAKE  -C part2        MAKE  -C part3   Since each line in a make target is run in its own shell  there is no need to worry about traversing back up the directory tree or to other directories   I suggest taking a look at the GNU make manual section 5 7  it is very helpful

User · Answer

You can add rules to your root Makefile in order to compile the necessary cpp files in other directories   The Makefile example below should be a good start in getting you to where you want to be    CC g   TARGET cppTest OTHERDIR       someotherpath in project src  SOURCE   cppTest cpp SOURCE     OTHERDIR  file cpp     End sources definition INCLUDE   -I     AN INCLUDE DIR    INCLUDE   -I   OTHERDIR     inc    end more includes  VPATH   OTHERDIR  OBJ   join   addsuffix    obj     dir   SOURCE       notdir   SOURCE  cpp  o         Fix dependency destination to be     dep relative to the src dir DEPENDS   join   addsuffix     dep     dir   SOURCE       notdir   SOURCE  cpp  d        Default rule executed all    TARGET           true     Clean Rule clean           -rm -f   TARGET    OBJ    DEPENDS       Rule for making the actual target   TARGET     OBJ           echo                          echo  Linking the target              echo                            CC    CFLAGS  -o         LIBS           echo -- Link finished --     Generic compilation rule   o     cpp          mkdir -p   dir              echo                          echo  Compiling   lt              CC    CFLAGS  -c   lt  -o         Rules for object files from cpp files    Object file for each file is put in obj directory    one level up from the actual source directory     obj   o     cpp          mkdir -p   dir              echo                          echo  Compiling   lt              CC    CFLAGS  -c   lt  -o       Rule for  other directory   You will need one per  other  dir   OTHERDIR     obj   o     cpp          mkdir -p   dir              echo                          echo  Compiling   lt              CC    CFLAGS  -c   lt  -o        Make dependancy rules     dep   d    cpp          mkdir -p   dir              echo                          echo Building dependencies file for    o            SHELL  -ec    CC  -M   CFLAGS    lt    sed  s    o    obj    o    gt          Dependency rule for  other  directory   OTHERDIR      dep   d    cpp          mkdir -p   dir              echo                          echo Building dependencies file for    o            SHELL  -ec    CC  -M   CFLAGS    lt    sed  s    o   OTHERDIR     obj    o    gt          Include the dependency files -include   DEPENDS

User · Answer

RC s post was SUPER useful  I never thought about using the   dir     function  but it did exactly what I needed it to do   In parentDir  have a bunch of directories with source files in them  dirA  dirB  dirC  Various files depend on the object files in other directories  so I wanted to be able to make one file from within one directory  and have it make that dependency by calling the makefile associated with that dependency    Essentially  I made one Makefile in parentDir that had  among many other things  a generic rule similar to RC s      o     cpp          mkdir -p   dir              echo                          echo  Compiling   lt              CC    CFLAGS  -c   lt  -o       Each subdirectory included this upper-level makefile in order to inherit this generic rule  In each subdirectory s Makefile  I wrote a custom rule for each file so that I could keep track of everything that each individual file depended on    Whenever I needed to make a file  I used  essentially  this rule to recursively make any all dependencies  Perfect    NOTE  there s a utility called  makepp  that seems to do this very task even more intuitively  but for the sake of portability and not depending on another tool  I chose to do it this way    Hope this helps

User · Answer

If the sources are spread in many folders  and it makes sense to have individual Makefiles then as suggested before  recursive make is a good approach  but for smaller projects I find it easier to list all the source files in the Makefile with their relative path to the Makefile like this     common sources COMMON SRC      main cpp                    src1 somefile cpp                    src1 somefile2 cpp                    src2 somefile3 cpp     I can then set VPATH this way   VPATH       src1    src2   Then I build the objects   COMMON OBJS      patsubst   cpp    ObjDir     ARCH   DEBUG  o    notdir   COMMON SRC      Now the rule is simple     the  common  object files   ObjDir     ARCH   DEBUG  o     cpp Makefile      echo creating              CXX    CFLAGS    EXTRA CFLAGS  -c -o      lt    And building the output is even easier     This will make the cbsdk shared library   BinDir    OUTPUTBIN     COMMON OBJS       echo building output           CXX  -o   BinDir    OUTPUTBIN    COMMON OBJS    LFLAGS    One can even make the VPATH generation automated by   VPATH      dir   COMMON SRC     Or using the fact that sort removes duplicates  although it should not matter    VPATH      sort    dir   COMMON SRC

User · Answer

If you have code in one subdirectory dependent on code in another subdirectory  you are probably better off with a single makefile at top-level   See Recursive Make Considered Harmful for the full rationale  but basically you want make to have the full information it needs to decide whether or not a file needs to be rebuilt  and it won t have that if you only tell it about a third of your project   The link above seems to be not reachable  The same document is reachable here    aegis sourceforge net lcgapp cern ch

User · Answer

Recursive Use of Make  all         MAKE  -C part1        MAKE  -C part2        MAKE  -C part3   This allows for make to split into jobs and use multiple cores

[linux] Makefiles with source files in different directories

Examples related to linux

Examples related to makefile