How to generate a Makefile with source in sub-directories using just one makefile

Question

I have source in a bunch of subdirectories like:

src/widgets/apple.cpp
src/widgets/knob.cpp
src/tests/blend.cpp
src/ui/flash.cpp

In the root of the project I want to generate a single Makefile using a rule like:

%.o: %.cpp
   $(CC) -c $<

build/test.exe: build/widgets/apple.o build/widgets/knob.o build/tests/blend.o src/ui/flash.o
   $(LD) build/widgets/apple.o .... build/ui/flash.o -o build/test.exe

When I try this it does not find a rule for build/widgets/apple.o. Can I change something so that the %.o: %.cpp is used when it needs to make build/widgets/apple.o ?

User · Answer

Thing is    will include the entire  relative  path to the source file which is in turn used to construct the object name  and thus its relative path   We use                           rules to build the object files   OBJDIR 1    o    c        ECHO     lt  - gt           test -d   OBJDIR 1     mkdir -pm 775   OBJDIR 1       test -d    D     mkdir -pm 775    D       -  RM           CC    CFLAGS    CFLAGS 1    ALL FLAGS    ALL DEFINES    ALL INCLUDEDIRS   -I   -c   lt  -o      This creates an object directory with name specified in   OBJDIR 1  and subdirectories according to subdirectories in source   For example  assume objs as toplevel object directory   in Makefile   widget apple cpp tests blend cpp   results in following object directory   objs widget apple o objs tests blend o

User · Answer

This is another trick   In main  Makefile  define SRCDIR for each source dir and include  makef mk  for each value of SRCDIR   In each source dir put file  files mk  with list of source files and compile options for some of them   In main  Makefile  one can define compile options and exclude files for each value of SRCDIR   Makefile   PRG                prog-name  OPTIMIZE           -O2 -fomit-frame-pointer  CFLAGS    -finline-functions-called-once LDFLAGS    -Wl --gc-section --reduce-memory-overheads --relax    DEFAULT GOAL      hex  OBJDIR             obj  MK DIRS              OBJDIR    SRCDIR               include         makef mk  SRCDIR    crc CFLAGS crc    -DCRC8 BY TABLE -DMODBUS CRC BY TABLE ASFLAGS crc    -DCRC8 BY TABLE -DMODBUS CRC BY TABLE include makef mk                                                                    CC                 avr-gcc -mmcu   MCU TARGET  -I  OBJCOPY            avr-objcopy OBJDUMP            avr-objdump  C FLAGS              CFLAGS    REGS    OPTIMIZE  CPP FLAGS            CPPFLAGS    REGS    OPTIMIZE  AS FLAGS             ASFLAGS  LD FLAGS             LDFLAGS  -Wl -Map   OBJDIR    PRG  map   C OBJS               C SRC   c   OBJDIR    o  CPP OBJS             CPP SRC   cpp   OBJDIR    o  AS OBJS              AS SRC   S   OBJDIR    o   C DEPS               C OBJS     d  CPP DEPS             CPP OBJS     d  AS DEPS              AS OBJS     d   OBJS                 C OBJS    CPP OBJS    AS OBJS  DEPS                 C DEPS    CPP DEPS    AS DEPS    hex     PRG  hex lst     PRG  lst     OBJDIR    PRG  elf     OBJS        CC    C FLAGS    LD FLAGS     -o       lst    OBJDIR    elf     - rm    2 gt   dev nul       OBJDUMP  -h -s -S   lt   gt        hex    OBJDIR    elf     - rm    2 gt   dev nul       OBJCOPY  -j  text -j  data -O ihex   lt         C OBJS      OBJDIR    o     c Makefile       CC  -MMD -MF    p d -c   C FLAGS    C FLAGS   call clear name   lt      lt  -o         sed -e  s     SRC FILES     g   lt     p d  gt     d      sed -e     s       subst        dir   lt   files mk n    lt     p d  gt  gt     d      sed -e  s              -e  s     t      -e  s          -e  s          lt     p d  gt  gt     d     - rm -f    p d    CPP OBJS      OBJDIR    o     cpp Makefile       CC  -MMD -MF    p d -c   CPP FLAGS    CPP FLAGS   call clear name   lt      lt  -o         sed -e  s     SRC FILES     g   lt     p d  gt     d      sed -e     s       subst        dir   lt   files mk n    lt     p d  gt  gt     d      sed -e  s              -e  s     t      -e  s          -e  s          lt     p d  gt  gt     d     - rm -f    p d    AS OBJS      OBJDIR    o     S Makefile       CC  -MMD -MF    p d -c   AS FLAGS    AS FLAGS   call clear name   lt      lt  -o         sed -e  s     SRC FILES     g   lt     p d  gt     d      sed -e     s       subst        dir   lt   files mk n    lt     p d  gt  gt     d      sed -e  s              -e  s     t      -e  s          -e  s          lt     p d  gt  gt     d     - rm -f    p d   clean      - rm -rf   OBJDIR    PRG  elf     - rm -rf   PRG  lst   OBJDIR    PRG  map     - rm -rf   PRG  hex   PRG  bin   PRG  srec     - rm -rf   PRG  eeprom hex   PRG  eeprom bin   PRG  eeprom srec     - rm -rf   MK DIRS       o    MK DIRS       o d      - rm -f tags cscope out      -rm -rf   OBJDIR        -rm -rf   OBJDIR      -rm   PRG    tag  tags tags    SRC FILES      if   -e tags     then ctags -u      else ctags      fi     cscope -U -b        include dep  files ifneq    MAKECMDGOALS    clean  -include   DEPS  endif     Create directory   shell mkdir   MK DIRS  2 gt  dev null    makef mk  SAVE C SRC      C SRC  SAVE CPP SRC      CPP SRC  SAVE AS SRC      AS SRC   C SRC    CPP SRC    AS SRC      include   SRCDIR  files mk MK DIRS      OBJDIR    SRCDIR    clear name     subst       1     define rename var   2    call clear name   SRCDIR     call clear name   1                subst      2     call clear name   SRCDIR        call clear name   1      call clear name   1      endef   define proc lang  ORIGIN SRC FILES        1  SRC   ifneq    strip     1  ONLY FILES       1  SRC      filter     1  ONLY FILES      1  SRC   else  ifneq    strip   ONLY FILES       1  SRC      filter   ONLY FILES      1  SRC   else   1  SRC      filter-out   EXCLUDE FILES      1  SRC   endif  endif    1  ONLY FILES      foreach name     1  SRC    eval   call rename var   name    1  FLAGS      foreach name   ORIGIN SRC FILES    eval   call clear name   name         endef     foreach lang C CPP AS    eval   call proc lang   lang       EXCLUDE FILES    ONLY FILES      SAVE C SRC      C SRC     SRCDIR     SAVE CPP SRC      CPP SRC     SRCDIR     SAVE AS SRC      AS SRC     SRCDIR      C SRC      SAVE C SRC  CPP SRC      SAVE CPP SRC  AS SRC      SAVE AS SRC      files mk  C SRC      main c CPP SRC    AS SRC     timer S  main c    -DDEBUG     crc files mk  C SRC       byte-modbus-crc c byte-crc8 c AS SRC      modbus-crc S crc8 S modbus-crc-table S crc8-table S  byte-modbus-crc c    --std gnu99 byte-crc8 c          --std gnu99

User · Answer

This will do it without painful manipulation or multiple command sequences:

build/%.o: src/%.cpp
src/%.o: src/%.cpp
%.o:
    $(CC) -c $< -o $@

build/test.exe: build/widgets/apple.o build/widgets/knob.o build/tests/blend.o src/ui/flash.o
    $(LD) $^ -o $@

JasperE has explained why "%.o: %.cpp" won't work; this version has one pattern rule (%.o:) with commands and no prereqs, and two pattern rules (build/%.o: and src/%.o:) with prereqs and no commands. (Note that I put in the src/%.o rule to deal with src/ui/flash.o, assuming that wasn't a typo for build/ui/flash.o, so if you don't need it you can leave it out.)

build/test.exe needs build/widgets/apple.o,
build/widgets/apple.o looks like build/%.o, so it needs src/%.cpp (in this case src/widgets/apple.cpp),
build/widgets/apple.o also looks like %.o, so it executes the CC command and uses the prereqs it just found (namely src/widgets/apple.cpp) to build the target (build/widgets/apple.o)

User · Answer

This is another trick   In main  Makefile  define SRCDIR for each source dir and include  makef mk  for each value of SRCDIR   In each source dir put file  files mk  with list of source files and compile options for some of them   In main  Makefile  one can define compile options and exclude files for each value of SRCDIR   Makefile   PRG                prog-name  OPTIMIZE           -O2 -fomit-frame-pointer  CFLAGS    -finline-functions-called-once LDFLAGS    -Wl --gc-section --reduce-memory-overheads --relax    DEFAULT GOAL      hex  OBJDIR             obj  MK DIRS              OBJDIR    SRCDIR               include         makef mk  SRCDIR    crc CFLAGS crc    -DCRC8 BY TABLE -DMODBUS CRC BY TABLE ASFLAGS crc    -DCRC8 BY TABLE -DMODBUS CRC BY TABLE include makef mk                                                                    CC                 avr-gcc -mmcu   MCU TARGET  -I  OBJCOPY            avr-objcopy OBJDUMP            avr-objdump  C FLAGS              CFLAGS    REGS    OPTIMIZE  CPP FLAGS            CPPFLAGS    REGS    OPTIMIZE  AS FLAGS             ASFLAGS  LD FLAGS             LDFLAGS  -Wl -Map   OBJDIR    PRG  map   C OBJS               C SRC   c   OBJDIR    o  CPP OBJS             CPP SRC   cpp   OBJDIR    o  AS OBJS              AS SRC   S   OBJDIR    o   C DEPS               C OBJS     d  CPP DEPS             CPP OBJS     d  AS DEPS              AS OBJS     d   OBJS                 C OBJS    CPP OBJS    AS OBJS  DEPS                 C DEPS    CPP DEPS    AS DEPS    hex     PRG  hex lst     PRG  lst     OBJDIR    PRG  elf     OBJS        CC    C FLAGS    LD FLAGS     -o       lst    OBJDIR    elf     - rm    2 gt   dev nul       OBJDUMP  -h -s -S   lt   gt        hex    OBJDIR    elf     - rm    2 gt   dev nul       OBJCOPY  -j  text -j  data -O ihex   lt         C OBJS      OBJDIR    o     c Makefile       CC  -MMD -MF    p d -c   C FLAGS    C FLAGS   call clear name   lt      lt  -o         sed -e  s     SRC FILES     g   lt     p d  gt     d      sed -e     s       subst        dir   lt   files mk n    lt     p d  gt  gt     d      sed -e  s              -e  s     t      -e  s          -e  s          lt     p d  gt  gt     d     - rm -f    p d    CPP OBJS      OBJDIR    o     cpp Makefile       CC  -MMD -MF    p d -c   CPP FLAGS    CPP FLAGS   call clear name   lt      lt  -o         sed -e  s     SRC FILES     g   lt     p d  gt     d      sed -e     s       subst        dir   lt   files mk n    lt     p d  gt  gt     d      sed -e  s              -e  s     t      -e  s          -e  s          lt     p d  gt  gt     d     - rm -f    p d    AS OBJS      OBJDIR    o     S Makefile       CC  -MMD -MF    p d -c   AS FLAGS    AS FLAGS   call clear name   lt      lt  -o         sed -e  s     SRC FILES     g   lt     p d  gt     d      sed -e     s       subst        dir   lt   files mk n    lt     p d  gt  gt     d      sed -e  s              -e  s     t      -e  s          -e  s          lt     p d  gt  gt     d     - rm -f    p d   clean      - rm -rf   OBJDIR    PRG  elf     - rm -rf   PRG  lst   OBJDIR    PRG  map     - rm -rf   PRG  hex   PRG  bin   PRG  srec     - rm -rf   PRG  eeprom hex   PRG  eeprom bin   PRG  eeprom srec     - rm -rf   MK DIRS       o    MK DIRS       o d      - rm -f tags cscope out      -rm -rf   OBJDIR        -rm -rf   OBJDIR      -rm   PRG    tag  tags tags    SRC FILES      if   -e tags     then ctags -u      else ctags      fi     cscope -U -b        include dep  files ifneq    MAKECMDGOALS    clean  -include   DEPS  endif     Create directory   shell mkdir   MK DIRS  2 gt  dev null    makef mk  SAVE C SRC      C SRC  SAVE CPP SRC      CPP SRC  SAVE AS SRC      AS SRC   C SRC    CPP SRC    AS SRC      include   SRCDIR  files mk MK DIRS      OBJDIR    SRCDIR    clear name     subst       1     define rename var   2    call clear name   SRCDIR     call clear name   1                subst      2     call clear name   SRCDIR        call clear name   1      call clear name   1      endef   define proc lang  ORIGIN SRC FILES        1  SRC   ifneq    strip     1  ONLY FILES       1  SRC      filter     1  ONLY FILES      1  SRC   else  ifneq    strip   ONLY FILES       1  SRC      filter   ONLY FILES      1  SRC   else   1  SRC      filter-out   EXCLUDE FILES      1  SRC   endif  endif    1  ONLY FILES      foreach name     1  SRC    eval   call rename var   name    1  FLAGS      foreach name   ORIGIN SRC FILES    eval   call clear name   name         endef     foreach lang C CPP AS    eval   call proc lang   lang       EXCLUDE FILES    ONLY FILES      SAVE C SRC      C SRC     SRCDIR     SAVE CPP SRC      CPP SRC     SRCDIR     SAVE AS SRC      AS SRC     SRCDIR      C SRC      SAVE C SRC  CPP SRC      SAVE CPP SRC  AS SRC      SAVE AS SRC      files mk  C SRC      main c CPP SRC    AS SRC     timer S  main c    -DDEBUG     crc files mk  C SRC       byte-modbus-crc c byte-crc8 c AS SRC      modbus-crc S crc8 S modbus-crc-table S crc8-table S  byte-modbus-crc c    --std gnu99 byte-crc8 c          --std gnu99

User · Answer

The reason is that your rule    o    cpp              expects the  cpp file to reside in the same directory as the  o your building  Since test exe in your case depends on build widgets apple o  etc   make is expecting apple cpp to be build widgets apple cpp   You can use VPATH to resolve this   VPATH   src widgets  BUILDDIR   build widgets    BUILDDIR    o    cpp             When attempting to build  build widgets apple o   make will search for apple cpp in VPATH  Note that the build rule has to use special variables in order to access the actual filename make finds     BUILDDIR    o    cpp           CC    lt  -o      Where    lt   expands to the path where make located the first dependency   Also note that this will build all the  o files in build widgets  If you want to build the binaries in different directories  you can do something like  build widgets   o    cpp               build ui   o    cpp               build tests   o    cpp                I would recommend that you use  canned command sequences  in order to avoid repeating the actual compiler build rule   define cc-command   CC    CFLAGS    lt  -o    endef   You can then have multiple rules like this   build1 foo o build1 bar o    o    cpp       cc-command   build2 frotz o build2 fie o    o    cpp       cc-command

User · Answer

Usually  you create a Makefile in each subdirectory  and write in the top-level Makefile to call make in the subdirectories    This page may help  http   www gnu org software make

User · Answer

This does the trick   CC           g   LD           g    MODULES      widgets test ui SRC DIR        addprefix src    MODULES   BUILD DIR      addprefix build    MODULES    SRC            foreach sdir   SRC DIR    wildcard   sdir    cpp   OBJ            patsubst src   cpp build   o   SRC   INCLUDES       addprefix -I   SRC DIR    vpath   cpp   SRC DIR   define make-goal  1   o    cpp       CC    INCLUDES  -c    lt  -o     endef   PHONY  all checkdirs clean  all  checkdirs build test exe  build test exe    OBJ        LD     -o      checkdirs    BUILD DIR     BUILD DIR        mkdir -p     clean       rm -rf   BUILD DIR     foreach bdir   BUILD DIR    eval   call make-goal   bdir       This Makefile assumes you have your include files in the source directories  Also it checks if the build directories exist  and creates them if they do not exist   The last line is the most important  It creates the implicit rules for each build using the function make-goal  and it is not necessary write them one by one  You can also add automatic dependency generation  using Tromey s way

User · Answer

Here is my solution  inspired from Beta s answer  It s simpler than the other proposed solutions  I have a project with several C files  stored in many subdirectories  For example   src lib c src aa a1 c src aa a2 c src bb b1 c src cc c1 c   Here is my Makefile  in the src  directory      make       - gt  compile the shared library  libfoo so    make clean - gt  remove the library file and all object files   o    make all   - gt  clean and compile SONAME    libfoo so SRC       lib c               aa a1 c             aa a2 c             bb b1 c             cc c1 c   compilation options CFLAGS    -O2 -g -W -Wall -Wno-unused-parameter -Wbad-function-cast -fPIC   linking options LDFLAGS   -shared -Wl -soname   SONAME     how to compile individual object files OBJS        SRC  c  o   c o        CC    CFLAGS  -c   lt  -o      PHONY  all clean    library compilation   SONAME     OBJS    SRC        CC    OBJS    LDFLAGS  -o   SONAME     cleaning rule clean      rm -f   OBJS    SONAME        additional rule all  clean lib   This example works fine for a shared library  and it should be very easy to adapt for any compilation process

User · Answer

The reason is that your rule    o    cpp              expects the  cpp file to reside in the same directory as the  o your building  Since test exe in your case depends on build widgets apple o  etc   make is expecting apple cpp to be build widgets apple cpp   You can use VPATH to resolve this   VPATH   src widgets  BUILDDIR   build widgets    BUILDDIR    o    cpp             When attempting to build  build widgets apple o   make will search for apple cpp in VPATH  Note that the build rule has to use special variables in order to access the actual filename make finds     BUILDDIR    o    cpp           CC    lt  -o      Where    lt   expands to the path where make located the first dependency   Also note that this will build all the  o files in build widgets  If you want to build the binaries in different directories  you can do something like  build widgets   o    cpp               build ui   o    cpp               build tests   o    cpp                I would recommend that you use  canned command sequences  in order to avoid repeating the actual compiler build rule   define cc-command   CC    CFLAGS    lt  -o    endef   You can then have multiple rules like this   build1 foo o build1 bar o    o    cpp       cc-command   build2 frotz o build2 fie o    o    cpp       cc-command

User · Answer

Usually  you create a Makefile in each subdirectory  and write in the top-level Makefile to call make in the subdirectories    This page may help  http   www gnu org software make

User · Answer

Here is my solution  inspired from Beta s answer  It s simpler than the other proposed solutions  I have a project with several C files  stored in many subdirectories  For example   src lib c src aa a1 c src aa a2 c src bb b1 c src cc c1 c   Here is my Makefile  in the src  directory      make       - gt  compile the shared library  libfoo so    make clean - gt  remove the library file and all object files   o    make all   - gt  clean and compile SONAME    libfoo so SRC       lib c               aa a1 c             aa a2 c             bb b1 c             cc c1 c   compilation options CFLAGS    -O2 -g -W -Wall -Wno-unused-parameter -Wbad-function-cast -fPIC   linking options LDFLAGS   -shared -Wl -soname   SONAME     how to compile individual object files OBJS        SRC  c  o   c o        CC    CFLAGS  -c   lt  -o      PHONY  all clean    library compilation   SONAME     OBJS    SRC        CC    OBJS    LDFLAGS  -o   SONAME     cleaning rule clean      rm -f   OBJS    SONAME        additional rule all  clean lib   This example works fine for a shared library  and it should be very easy to adapt for any compilation process

User · Answer

Usually  you create a Makefile in each subdirectory  and write in the top-level Makefile to call make in the subdirectories    This page may help  http   www gnu org software make

User · Answer

The reason is that your rule    o    cpp              expects the  cpp file to reside in the same directory as the  o your building  Since test exe in your case depends on build widgets apple o  etc   make is expecting apple cpp to be build widgets apple cpp   You can use VPATH to resolve this   VPATH   src widgets  BUILDDIR   build widgets    BUILDDIR    o    cpp             When attempting to build  build widgets apple o   make will search for apple cpp in VPATH  Note that the build rule has to use special variables in order to access the actual filename make finds     BUILDDIR    o    cpp           CC    lt  -o      Where    lt   expands to the path where make located the first dependency   Also note that this will build all the  o files in build widgets  If you want to build the binaries in different directories  you can do something like  build widgets   o    cpp               build ui   o    cpp               build tests   o    cpp                I would recommend that you use  canned command sequences  in order to avoid repeating the actual compiler build rule   define cc-command   CC    CFLAGS    lt  -o    endef   You can then have multiple rules like this   build1 foo o build1 bar o    o    cpp       cc-command   build2 frotz o build2 fie o    o    cpp       cc-command

User · Answer

Thing is    will include the entire  relative  path to the source file which is in turn used to construct the object name  and thus its relative path   We use                           rules to build the object files   OBJDIR 1    o    c        ECHO     lt  - gt           test -d   OBJDIR 1     mkdir -pm 775   OBJDIR 1       test -d    D     mkdir -pm 775    D       -  RM           CC    CFLAGS    CFLAGS 1    ALL FLAGS    ALL DEFINES    ALL INCLUDEDIRS   -I   -c   lt  -o      This creates an object directory with name specified in   OBJDIR 1  and subdirectories according to subdirectories in source   For example  assume objs as toplevel object directory   in Makefile   widget apple cpp tests blend cpp   results in following object directory   objs widget apple o objs tests blend o

User · Answer

Usually  you create a Makefile in each subdirectory  and write in the top-level Makefile to call make in the subdirectories    This page may help  http   www gnu org software make

User · Answer

This does the trick   CC           g   LD           g    MODULES      widgets test ui SRC DIR        addprefix src    MODULES   BUILD DIR      addprefix build    MODULES    SRC            foreach sdir   SRC DIR    wildcard   sdir    cpp   OBJ            patsubst src   cpp build   o   SRC   INCLUDES       addprefix -I   SRC DIR    vpath   cpp   SRC DIR   define make-goal  1   o    cpp       CC    INCLUDES  -c    lt  -o     endef   PHONY  all checkdirs clean  all  checkdirs build test exe  build test exe    OBJ        LD     -o      checkdirs    BUILD DIR     BUILD DIR        mkdir -p     clean       rm -rf   BUILD DIR     foreach bdir   BUILD DIR    eval   call make-goal   bdir       This Makefile assumes you have your include files in the source directories  Also it checks if the build directories exist  and creates them if they do not exist   The last line is the most important  It creates the implicit rules for each build using the function make-goal  and it is not necessary write them one by one  You can also add automatic dependency generation  using Tromey s way

User · Answer

This will do it without painful manipulation or multiple command sequences:

build/%.o: src/%.cpp
src/%.o: src/%.cpp
%.o:
    $(CC) -c $< -o $@

build/test.exe: build/widgets/apple.o build/widgets/knob.o build/tests/blend.o src/ui/flash.o
    $(LD) $^ -o $@

JasperE has explained why "%.o: %.cpp" won't work; this version has one pattern rule (%.o:) with commands and no prereqs, and two pattern rules (build/%.o: and src/%.o:) with prereqs and no commands. (Note that I put in the src/%.o rule to deal with src/ui/flash.o, assuming that wasn't a typo for build/ui/flash.o, so if you don't need it you can leave it out.)

build/test.exe needs build/widgets/apple.o,
build/widgets/apple.o looks like build/%.o, so it needs src/%.cpp (in this case src/widgets/apple.cpp),
build/widgets/apple.o also looks like %.o, so it executes the CC command and uses the prereqs it just found (namely src/widgets/apple.cpp) to build the target (build/widgets/apple.o)

User · Answer

The reason is that your rule    o    cpp              expects the  cpp file to reside in the same directory as the  o your building  Since test exe in your case depends on build widgets apple o  etc   make is expecting apple cpp to be build widgets apple cpp   You can use VPATH to resolve this   VPATH   src widgets  BUILDDIR   build widgets    BUILDDIR    o    cpp             When attempting to build  build widgets apple o   make will search for apple cpp in VPATH  Note that the build rule has to use special variables in order to access the actual filename make finds     BUILDDIR    o    cpp           CC    lt  -o      Where    lt   expands to the path where make located the first dependency   Also note that this will build all the  o files in build widgets  If you want to build the binaries in different directories  you can do something like  build widgets   o    cpp               build ui   o    cpp               build tests   o    cpp                I would recommend that you use  canned command sequences  in order to avoid repeating the actual compiler build rule   define cc-command   CC    CFLAGS    lt  -o    endef   You can then have multiple rules like this   build1 foo o build1 bar o    o    cpp       cc-command   build2 frotz o build2 fie o    o    cpp       cc-command

[makefile] How to generate a Makefile with source in sub-directories using just one makefile

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