What does all stand for in a makefile

Question

I read some tutorials concerning Makefiles but for me it is still unclear for what the target  all  stands for and what it does   Any ideas

User · Accepted Answer

A build  as Makefile understands it  consists of a lot of targets   For example  to build a project you might need   Build file1 o out of file1 c Build file2 o out of file2 c Build file3 o out of file3 c Build executable1 out of file1 o and file3 o Build executable2 out of file2 o   If you implemented this workflow with makefile  you could make each of the targets separately   For example  if you wrote  make file1 o   it would only build that file  if necessary   The name of all is not fixed   It s just a conventional name   all target denotes that if you invoke it  make will build all what s needed to make a complete build   This is usually a dummy target  which doesn t create any files  but merely depends on the other files   For the example above  building all necessary is building executables  the other files being pulled in as dependencies   So in the makefile it looks like this   all  executable1 executable2   all target is usually the first in the makefile  since if you just write make in command line  without specifying the target  it will build the first target   And you expect it to be all   all is usually also a  PHONY target   Learn more here

User · Answer

The manual for GNU Make gives a clear definition for all in its list of standard targets   If the author of the Makefile is following that convention then the target all should    Compile the entire program  but not build documentation  Be the the default target     As in running just make should do the same as make all    To achieve 1 all is typically defined as a  PHONY target that depends on the executable s  that form the entire program    PHONY   all all   executable   To achieve 2 all should either be the first target defined in the make file or be assigned as the default goal    DEFAULT GOAL    all

User · Answer

The target  all  is an example of a dummy target - there is nothing on disk called  all   This means that when you do a  make all   make always thinks that it needs to build it  and so executes all the commands for that target  Those commands will typically be ones that build all the end-products that the makefile knows about  but it could do anything    Other examples of dummy targets are  clean  and  install   and they work in the same way   If you haven t read it yet  you should read the GNU Make Manual  which is also an excellent tutorial

User · Answer

Not sure it stands for anything special   It s just a convention that you supply an  all  rule  and generally it s used to list all the sub-targets needed to build the entire project  hence the name  all    The only thing special about it is that often times people will put it in as the first target in the makefile  which means that just typing  make  alone will do the same thing as  make all

[makefile] What does "all" stand for in a makefile?

Examples related to makefile