What do the makefile symbols and mean

Question

CC g   CFLAGS -c -Wall LDFLAGS  SOURCES main cpp hello cpp factorial cpp OBJECTS   SOURCES  cpp  o  EXECUTABLE hello  all    SOURCES    EXECUTABLE     EXECUTABLE     OBJECTS        CC    LDFLAGS    OBJECTS  -o      cpp o        CC    CFLAGS    lt  -o      What do the    and   lt  do exactly

User · Answer

The    and   lt  are special macros   Where      is the file name of the target     lt  is the name of the first dependency

User · Answer

is the name of the target being generated  and   lt  the first prerequisite  usually a source file   You can find a list of all these special variables in the GNU Make manual  For example  consider the following declaration  all  library cpp main cpp  In this case      evaluates to all   lt  evaluates to library cpp    evaluates to library cpp main cpp

User · Answer

in exemple if you want to compile sources but have objects in an different directory    You need to do    gcc -c -o  lt obj 1 o gt   lt srcs 1 c gt   lt obj 2 o gt   lt srcs 2 c gt        but with most of macros the result will be all objects followed by all sources  like    gcc -c -o  lt all OBJ path gt   lt all SRC path gt    so this will not compile anything    and you will not be able to put your objects files in a different dir     the solution is to use these special macros       lt    this will generate a  o file  obj file o  for each  c file in SRC  src file c     OBJ    SRC     gcc -c -o      lt    HEADERS    FLAGS    it means               OBJ        lt      SRC    but lines by lines INSTEAD of all lines of OBJ followed by all lines of SRC

User · Answer

The    and   lt  are called automatic variables  The variable    represents the name of the target and   lt  represents the first prerequisite required to create the output file  For example  hello o  hello c hello h          gcc -c   lt  -o     Here  hello o is the output file  This is what    expands to  The first dependency is hello c  That s what   lt  expands to  The -c flag generates the  o file  see man gcc for a more detailed explanation  The -o specifies the output file to create  For further details  you can read this article about Linux Makefiles  Also  you can check the GNU  make manuals  It will make it easier to make Makefiles and to debug them  If you run this command  it will output the makefile database  make -p

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The Makefile builds the hello executable if any one of main cpp  hello cpp  factorial cpp changed  The smallest possible Makefile to achieve that specification could have been   hello  main cpp hello cpp factorial cpp     g   -o hello main cpp hello cpp factorial cpp    pro  very easy to read con  maintenance nightmare  duplication of the C   dependencies con  efficiency problem  we recompile all C   even if only one was changed   To improve on the above  we only compile those C   files that were edited  Then  we just link the resultant object files together   OBJECTS main o hello o factorial o  hello    OBJECTS      g   -o hello   OBJECTS   main o  main cpp     g   -c main cpp  hello o  hello cpp     g   -c hello cpp  factorial o  factorial cpp     g   -c factorial cpp    pro  fixes efficiency issue con  new maintenance nightmare  potential typo on object files rules   To improve on this  we can replace all object file rules with a single  cpp o rule   OBJECTS main o hello o factorial o  hello    OBJECTS      g   -o hello   OBJECTS    cpp o      g   -c   lt  -o       pro  back to having a short makefile  somewhat easy to read   Here the  cpp o rule defines how to build anyfile o from anyfile cpp      lt  matches to first dependency  in this case  anyfile cpp    matches the target  in this case  anyfile o    The other changes present in the Makefile are    Making it easier to changes compilers from g   to any C   compiler  Making it easier to change the compiler options  Making it easier to change the linker options  Making it easier to change the C   source files and output  Added a default rule  all  which acts as a quick check to ensure all your source files are present before an attempt to build your application is made

User · Answer

From Managing Projects with GNU Make  3rd Edition  p  16  it s under GNU Free Documentation License       Automatic variables are set by make after a rule is matched  They   provide access to elements from the target and prerequisite lists so   you don   t have to explicitly specify any filenames  They are very   useful for avoiding code duplication  but are critical when defining   more general pattern rules       There are seven    core    automatic variables              The filename representing the target        The filename element of an archive member specification      lt   The filename of the first prerequisite        The names of all prerequisites that are newer than the target    separated by spaces        The filenames of all the prerequisites  separated by spaces  This   list has duplicate filenames removed since for most uses  such as   compiling  copying  etc   duplicates are not wanted        Similar to     this is the names of all the prerequisites separated   by spaces  except that    includes duplicates  This variable was   created for specific situations such as arguments to linkers where   duplicate values have meaning        The stem of the target filename  A stem is typically a filename   without its suffix  Its use outside of pattern rules is   discouraged          In addition  each of the above variables has two variants for   compatibility with other makes  One variant returns only the directory   portion of the value  This is indicated by appending a    D    to the   symbol     D      lt D   etc  The other variant returns only the file   portion of the value  This is indicated by appending an    F    to the   symbol     F      lt F   etc  Note that these variant names are more than   one character long and so must be enclosed in parentheses  GNU make   provides a more readable alternative with the dir and notdir   functions

[makefile] What do the makefile symbols $@ and $< mean?

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